The present invention relates to a silicon semiconductor substrate and, more particularly, to a silicon semiconductor substrate with an insulating layer embedded therein in which an insulating layer to form an electrically isolated semiconductor region is included therein and to a method for forming the same.
In monolithic semiconductor integrated circuits, as methods for forming an isolated region to isolate a semiconductor element or elements from another element or other elements, methods whereby a reverse-biased P-N junction is used or methods whereby an insulating layer is used are adopted. One of the methods whereby the P-N junction is used is shown in FIG. 1. In FIG. 1, N.sup.- -type monocrystalline silicon layer 2 is epitaxially grown on a P.sup.- -type monocrystalline silicon substrate 1. A P.sup.+ -type diffusion layer 3 is formed by selectively diffusing P-type impurities of a high concentration such that the layer 3 reaches from the upper surface of the monocrystalline layer 2 to the silicon substrate 1. An N.sup.- -type silicon layer 4 (isolated region) surrounded by the diffusion layer 3 (isolating region) and the silicon substrate 1 is electrically isolated from other semiconductor regions by applying a reverse bias to the P-N junction. A predetermined semiconductor element or elements are formed in the N.sup.- -type silicon layer 4. Although the isolated region 4 shown in FIG. 1 can be cheaply realized, there is a drawback such that the area to form the P.sup.+ -type diffusion layer 3, namely, the isolating region becomes large.
To solve the drawback in FIG. 1, a method whereby an isolated region is formed as shown in FIG. 2 is known. In FIG. 2, a P.sup.+ -type high concentration layer 5 is formed in the P.sup.- -type silicon substrate 1 by way of an ion implantation. Thereafter, similarly to FIG. 1, the N- epitaxial layer 2 is formed on the substrate 1 and a P.sup.+ -type diffusion layer 7 is formed from the upper surface of this epitaxial layer by way of a diffusion. By applying a reverse bias to the P-N junction formed in this way, the isolated N.sup.- -type region 4 is formed. The P.sup.+ -type diffusion layer 7 is formed by way of the diffusion from the upper surface into the epitaxial layer 2 and the diffusion from the P.sup.+ -type high concentration layer 5; therefore, there are advantages such that the layer 7 is formed in a short time and the widths in the lateral direction of the isolating regions 5 and 7 can be made small. However, in FIG. 2, the circuit to apply the reverse bias potential to the P-N junction is needed and a leak current in the P-N junction exerts an influence on the characteristic of the semiconductor element formed in the isolated region 4. Even in FIG. 2 as well, the area of the isolating region cannot be made sufficiently small and also it is improper to form a high voltage semiconductor element in the isolated region.
As one of the methods whereby an insulating layer is used to form an isolated region, a structure as shown in FIG. 3 is known. In FIG. 3, the N.sup.- layer 2 is epitaxially grown on the upper surface of the P.sup.- -type silicon substrate 1. A groove 10 is formed so as to reach from the main surface (free surface) of the N.sup.- layer 2 to the P.sup.- -type substrate 1. After a thermal silicon dioxide layer 11 was formed on the inner surface of the groove 10, a polycrystalline silicon material 12 in which no impurity is doped is embedded into the groove 10. According to this method, the isolating region area to form the isolated region 4 can be made small. However, to electrically isolate the isolated region 4, a circuit to apply a reverse bias between the N.sup.- region 4 and the P.sup.- substrate 1 is needed and also a leak current is generated through this P-N junction.
FIGS. 4A and 4B show a well-known method whereby an isolated region is formed by only an insulating layer, In FIG. 4A, a groove 15 is formed by performing a selective etching to a predetermined region of an N-type silicon substrate 14. Further, a silicon dioxide layer 16 is formed on the surface of the groove 15. A polycrystalline silicon layer 17 in which no impurity is doped is formed on the silicon dioxide layer 16. Next, the N-type silicon substrate 14 is ground until it reaches from its free surface to the groove 15. Thus, an isolated region 18 surrounded by the silicon dioxide layer 16 is formed as an island region. However, the semiconductor substrate shown in FIGS. 4A and 4B is insulated by the free surface (upper surface) of the N-type silicon substrate 14, the free surface (lower surface) of the polycrystalline silicon layer 17, and the silicon dioxide layer 16. Consequently, the polycrystalline silicon layer 17 cannot be used as a path of a current and also such a semiconductor substrate becomes expensive.